This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-095969, filed Mar. 29, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device including a high breakdown voltage semiconductor device such as a punch-through type IGBT (PT-IGBT) and a method of manufacturing the same.
2. Description of the Related Art
An IGBT (Insulated Gate Bipolar Transistor) is known to the art as one of high breakdown voltage semiconductor devices. FIG. 5 is a cross sectional view showing a structure of a conventional punch-through type IGBT. As shown in the drawing, the IGBT comprises an nxe2x88x92-type base layer 81. A p-type base layer 82 is formed in the nxe2x88x92-type base layer 81. Also, an n-type emitter layer 83 is formed in the p-type base layer 82.
A gate electrode 85 is provided through a gate insulating film 84 on the p-type base layer 82 sandwiched between the n-type emitter layer 83 and the nxe2x88x92-type base layer 81. The gate electrode 85 is formed of, for example, polycrystalline silicon (polysilicon).
An emitter electrode 86 is connected to the n-type emitter layer 83 and the p-type base layer 82 through contact holes formed in an interlayer insulating film 87. The emitter electrode 86 is formed of a metal such as Al. Further, the surface of the nxe2x88x92-type base layer 81 including the gate electrode 85 and the emitter electrode 86 is covered with a passivation film (not shown).
On the other hand, a p+-type collector layer 89 is formed on the back surface of the nxe2x88x92-type base layer 81 through an nxe2x88x92-type buffer layer 88. A collector electrode 90 is formed on the surface of the p+-type collector layer 89. The collector electrode 90 is formed of a metal such as Al.
However, the PT-IGBT of this type gives rise to a serious problem as described in the following. Specifically, the PT-IGBT shown in FIG. 5 is manufactured by using a thick epitaxial wafer having the n+-type buffer layer 88 and the nxe2x88x92-type base layer 81 previously formed on the p+-type collector layer 89.
To be more specific, the n+-type buffer layer 88 having a thickness of 15 xcexcm and the nxe2x88x92-type base layer 81 having a thickness of 60 xcexcm are successively formed by the epitaxial growth method on the p+-type collector layer 89 having a thickness of 625 xcexcm to form an epitaxial wafer having a thickness of 700 xcexcm. Then, the back surface of the p+-type collector layer 89 is polished to decrease the thickness of the p+-type collector layer 89 to 175 xcexcm, thereby using the epitaxial wafer as a substrate.
However, it is costly to prepare the epitaxial wafer having a thickness of 700 xcexcm, with the result that the PT-IGBT shown in FIG. 5 is rendered costly.
In order to overcome the problem pointed out above, the present inventors have taken it into consideration to use an ordinary wafer in which the n+-type buffer layer 88 and the p+-type collector layer 89 are not formed therein in advance.
To be more specific, the inventors tried to use the ordinary wafer prepared by the method which includes successively forming the p-type base layer 82, the n-type emitter layer 83, the gate insulating film 84, the gate electrode 85, the interlayer insulating film 87, the emitter electrode 86, and a passivation layer (not shown) on the surface of a wafer in the order mentioned, successively implanting n-type impurity ions and p-type impurity ions into the back surface of the nxe2x88x92-type base layer 81, and irradiating the back surface of the nxe2x88x92-type base layer 81 with a laser beam for activating these n-type and p-type impurities thereby to form the n+-type buffer layer 88 and the p+-type collector 89.
However, since the melting depth achieved by the laser irradiation (laser annealing) of this kind is only several microns, and the irradiation time is short, the heat generated by the laser irradiation is not sufficiently transmitted into the n+-type buffer layer 88 so as to cause a damage layer derived from, for example, the ion implantation to remain in the n+-type buffer layer 88. As a result, the saturation voltage between the collector and the emitter (VCE (sat)) is increased under the on-state of the device, and the lowering of the characteristics that the leak current is generated takes place under the off-state of the device.
The saturation voltage VCE (sat) is increased because the damaged layer acts as a trap of the injected holes. On the other hand, the leak current is generated because, if the damaged layer 91 is depleted, the damaged layer 91 acts as the generation center of the carrier under the off-state, as shown in FIG. 6.
As a technique for eliminating the problem derived from the presence of the residual damaged layer, it is considered effective to decrease the acceleration energy of the n-type impurity implanted into the n+-type buffer layer 88 because the activation rate of the n-type impurity is increased with decrease in the acceleration energy Vacc as shown in FIG. 7.
It should be noted that, if the acceleration energy of the n-type impurity is decreased, the depth of the n+-type buffer layer 88 is decreased, with the result that the impurity concentration profile within the n+-type buffer layer 88 is greatly affected by the diffusion of the p+-type impurity to lower the controllability of the concentration profile.
If the controllability of the concentration profile is lowered, a serious problem is brought about as follows. Specifically, if the controllability of the concentration profile is lowered, it is rendered difficult or impossible to form the n+-type buffer layer 88 and the p+-type collector layer 89 each having a desired concentration profile. As a result, it is impossible to obtain desired device characteristics. Also, the devices are rendered different from each other in the concentration profile, leading to nonuniformity in the device characteristics.
At any rate, the n+-type buffer layer and the p+-type collector layer are formed by the ion implantation and the laser annealing in the conventional PT-IGBT of this type, with the result that the saturation voltage VCE(sat) is increased and the controllability of the impurity concentration profile in the n+-type buffer layer is lowered.
According to a first aspect of the present invention, there is provided a semiconductor device, which comprises a first base layer having a first conductivity type, the base layer having first and second surfaces and further having a high resistance; a second base layer, provided in the first surface, having a second conductivity type; an emitter layer, provided in the second base layer, having the first conductivity type; a gate electrode provided through a gate insulating film over the second base layer disposed between the emitter layer and the first base layer; a buffer layer, formed in the second surface, having the first conductivity type and further having a high impurity concentration; a first activation rate, defined by an activated first conductivity type impurity density [cmxe2x88x922] in the buffer layer due to SR analysis/a first conductivity type impurity density [cmxe2x88x922] in the buffer layer due to SIMS analysis, being 25% or more; a collector layer, provided in the buffer layer, having the second conductivity type; and a second activation rate, defined by an activated second conductivity type impurity density [cmxe2x88x922] in the collector layer due to SR analysis/a second conductivity type impurity density [cmxe2x88x922] in the collector layer due to SIMS analysis, being more than 0% and 10% or less.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises preparing a first base layer having a first conductivity type and also having first and second surfaces each having a high resistance; successively forming an insulating film providing a gate insulating film and a conductive film providing a gate electrode on the first surface of the first base layer in the order mentioned; successively patterning the conductive film and the insulating film so as to expose partly the first surface; forming a second base layer having a second conductivity type in the exposed first surface by self-alignment; selectively forming an emitter layer having the first conductivity type in the second base layer; forming an emitter electrode on the emitter layer; implanting first impurity ions having the first conductivity type into the second surface of the first base layer; activating the first impurity ions by a first annealing treatment so as to form a buffer layer having a high impurity concentration and also having the first conductivity type on the second surface; implanting second impurity ions having the second conductivity type into a surface region of the buffer layer; and activating the second impurity ions by a second annealing treatment so as to form a collector layer having the second conductivity type in the buffer layer.